Memory devices such as a Synchronous Dynamic Random Access Memory (SDRAM) and memory controllers for transmitting and receiving data to and from the memory devices employ a source synchronous scheme to transmit data in order to meet a demand for high-speed data transmission. In the source synchronous scheme, a strobe signal and data can be transmitted and received together.
When a memory controller receives data from a memory device in a system which uses the source synchronous scheme for data transmission, for example, timing between a strobe signal and data is adjusted so that the data can be received in a valid duration of the data based on the strobe signal.
In the timing adjustment, data valid duration, in which data can be stably received when a strobe signal is used to receive the data, is made shorter as a frequency for data transmission is higher. Furthermore, the timing needs to be flexibly adjusted, since the relationship between the data and the strobe signal changes due to process characteristics, temperature change, and voltage change.
Hence, a conventional data receiving circuit synchronizes timing between a strobe signal and data, using, for example, a delay element (See Patent Literature 1). Moreover, the conventional data receiving circuit allows the delay element to vary the amount of delay.
Typically, in order to find an amount of delay to be used for stable data transmission, the memory controller first sets an amount of delay, writes data to a memory device, and reads the data from the memory device. Then, the memory controller checks whether or not the read data corresponds to the written data to determine whether or not the set amount of delay can be used for data transmission. The memory controller repeats such operations to detect a window−that is a time period for the amount of delay−during which stable data transmission can be executed.
Moreover, in order to keep the above-determined amount of delay constant during an operation of the system, the memory controller always monitors, based on a phase of an internal clock, whether or not there is a change in an amount of delay to be used as a reference. Then, in the case where the change is found in the reference amount of delay, the memory controller reflects the change in an amount of delay to be used for the above-described timing adjustment.
In a typical delay element, however, a change in a delay setting value indicating a delay amount inevitably generates noise onto the output provided from the delay element. Hence, the delay setting value cannot be changed during transmission and reception of data. Thus, in the SDRAM, the delay setting value is changed when a refresh command is executed. This is because data is not transmitted or received during the execution (See Patent Literature 2). In such a system, the refresh command is executed only for every certain period. Even though the amount of delay changes during the period, the system cannot reflect the change in the delay setting value. The failure in reflection causes a problem in that a gap develops between the amount of delay for the delay element and the optimum amount of delay, which deteriorates stability of high-speed data transmission.
A conventional technique allows a delay setting value to be reflected not only during a refresh operation but also during a non-read operation, which is a write operation, as far as the delay element is used for reading (See PTL 2). Hence, the conventional technique can update more often the amount of delay for the delay element.
Another conventional technique discloses changing an amount of delay by adding a capacitance to a signaling pathway and switching between the validity and invalidity of the addition (See Patent Literature 3). Hence, the conventional technique can reduce noise which appears when the amount of delay is changed during the operation. Thus, the conventional technique can update the amount of delay during the operation, which allows the amount of delay to be updated more often.